Self-aligned multiple patterning (SAMP) techniques (such as self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP)) are currently used in ultra-high density integrated circuits to provide an electrical interconnection system which includes multiple arrays of parallel metal lines disposed in several levels of dielectric layers. The dielectric layers are typically interconnected through a system of metalized vias. Conventionally, within an array of metal lines, the direction longitudinal, or parallel, to the metal lines is designated the “Y” direction and the direction perpendicular, or lateral, to the metal lines is designated the “X” direction.
However, formation of interconnect systems having large arrays of multiple parallel metal lines in a Back-End-Of-Line (BEOL) process flow for a semiconductor fabrication often require the metal lines to have both variable pitch and variable line widths. This kind of variability in both pitch and line width is very difficult to achieve with a conventional SAMP process. This is particularly the case when the pitch (i.e., the minimum distance between repetitive features in a semiconductor device structure) is less than or equal to 38 nm.
Typically, an interconnect system located in the back end, or BEOL portion, of a semiconductor structure will be composed of many cells of repetitive arrays of lines, wherein the overall height of each cell (i.e., the overall X direction distance across the cell) is an integer multiple of a minimum pitch, or track. The track (or minimum pitch) being equal to the minimum functionally allowable line width (in the X direction) plus the minimum space (in the X direction) between the lines. For example, a five track cell in an interconnection system where the minimum pitch is 36 nm would have an overall height that is five times 36 nm, for a total of 180 nm. By way of another example, a six track cell having a minimum pitch of 28 nm would have an overall height of six times 28 nm, for a total of 168 nm.
However, within those cells, different lines will have different functions and, therefore, will require different line widths. For example, power lines within a typical cell are primarily used to deliver power to devices (such as transistors) in a semiconductor structure and signal lines within that same cell are used to carry signals to and from the semiconductor devices. Since the power lines must carry much more current than the signal lines, the power lines must be significantly wider than the signal lines and therefore require a larger pitch. This type of variability is difficult to achieve in a conventional SAMP process.
Additionally, if the spaces between metal lines in a cell of a semiconductor interconnect system become too narrow due to, for example, lithographic variability, those unacceptably small spaces can lead to time delayed shorting between the lines. Time delayed shorting, or Time Delayed Dielectric Breakdown (TDDB), can occur when the spaces between lines become so small that the dielectric isolating material between the lines becomes stressed over an extended period of time by the electric fields being generated between the lines.
Additionally, in order to provide functionality between devices, such as transistors, capacitors and the like, in the integrated circuit, a plurality of continuity cuts (also referred to as continuity blocks) must be lithographically patterned into the signal lines and power lines of the cells at specific locations to direct current flow between the dielectric layers and the devices. Problematically however, lithographic misalignment, or overlay, is a significant issue at lower technology node sizes, such as when the technology class size is no greater than 10 nm or when the repetitive pitch distance is no greater than 38 nm. Overlay is a measure of how well two lithographic layers (or steps) align. Overlay can be in the X or Y direction and is expressed in units of length.
The lithographically disposed continuity cuts must be large enough to make sure that they cut the signal line or power line they are supposed to without clipping any neighboring lines, taking into account worst case overlay tolerance conditions. However, for a pitch of 38 nm or less, the current state of the art overlay control is not precise enough to prevent continuity cuts from over-extending into neighboring lines. The unwanted over-extension of continuity cuts into neighboring lines can, in the worst case condition, completely interrupt electrical continuity in the wrong line.
Additionally, a line that is inadvertently only partially cut (or notched) may still conduct for a time, but may over heat and prematurely fail over time. This inadvertent cutting and/or notching is particularly problematic for signal lines, which are much smaller in horizontal width than power lines.
Accordingly, there is a need for an apparatus, and method of forming the same, of cells of an interconnect system for a semiconductor structure, wherein the spaces between lines within the cell are not subject to lithographic variability. Additionally, there is a need for the lines within the cells to be variable in width and variable in pitch. There is a need, specifically, for such variable line widths and pitches where the cells have a track (or minimum pitch between lines) of 38 nm or less.
Additionally, there is a need for a method of patterning continuity cuts (or continuity blocks) within signal lines and power lines of the cells that are tolerant of lithographic misalignment. More specifically, there is a need for a method that is capable of patterning continuity cuts into the signal lines and power lines of the cells such that the cuts at least do not inadvertently fully cut any of the neighboring lines and do not notch any of the neighboring signal lines.